Integrated circuits or chips are made up of millions of active and passive devices such as transistors and capacitors. These devices are initially isolated from each other, and are later interconnected to form integrated circuits. Connector structures are further formed for integrated circuits, which may include bond pads or metal bumps formed on the surface of the circuits. Electrical connections are made through the bond pads or metal bumps to connect the chip to a package substrate or another die. In general, chips may be assembled into a package such as a pin grid array (PGA), or ball grid array (BGA), using wire bonding (WB) or flip chip (FC) packaging technology.
A flip-chip (FC) packaging technology may connect a chip to a package substrate using a bump-on-trace (BOT) structure, wherein the connections are made through the metal bumps to connect the chip to the metal traces of the package substrate or die. The BOT structure offers a low cost alternative to microelectronic packaging industry. However, the reliability issues for BOT structure rises as substrate structure goes thinner.
When using a BOT structure, bumps for the chip are soldered onto the trace on the package substrate by a reflow process. When the bumps are joined to the substrate and cooled down from the reflow condition to a room temperature, thermal force caused by coefficient of thermal expansion (CTE) mismatch drives the substrate shrinkage and leads to relative twist on each bump. Once stress level rises over the adhesive criteria between the substrate and the trace, a trace peeling failure occurs.